1. Technical Field
The embodiments described herein relate to an apparatus and a method for generating resistance calibration codes for use in a semiconductor integrated circuit.
2. Related Art
Resistance calibration codes are used to cope with a PVT (Process, Voltage, and Temperature) fluctuation by controlling on-resistance and on-die termination (ODT) and these codes are controlled by a resistance calibration code generating apparatus.
FIG. 1 is a block diagram illustrating a conventional resistance calibration code generating apparatus in a semiconductor integrated circuit.
As shown in FIG. 1, the conventional resistance calibration code generating apparatus includes a code calibration unit 10 and a state machine 20.
The code calibration unit 10 is configured to output resistance calibration codes ‘PCODE<0:N>’ and ‘NCODE<0:N>’ using code calibration time control commands ‘ZQINIT’, ‘ZQOPER’ and ‘ZQCS’, a delayed clock signal ‘CLKD’, and a reference voltage ‘VREF’. The code calibration unit 10 is connected to an external resistor RZQ through a ZQ pin.
The state machine 20 is configured to selectively activate the code calibration time control commands ‘ZQINIT’, ‘ZQOPER’ and ‘ZQCS’ using an external clock ‘CLK’ according to logic levels of a code calibration command ‘ZQC’ and an address signal ‘A10’. A reset signal ‘RST’ is used as an initialization signal to initialize the state machine 20.
An operation of the code calibration is executed in an idle state of the semiconductor integrated circuit.
After the code calibration command ‘ZQC’ is activated, the state machine 20 generates the code calibration time control commands ‘ZQINIT’, ‘ZQOPER’ and ‘ZQCS’ based on the external clock ‘CLK’. The code calibration time control commands ‘ZQINIT’, ‘ZQOPER’ and ‘ZQCS’ are produced in synchronization with the external clock ‘CLK’.
The code calibration time control command ‘ZQINIT’ is activated when both the code calibration command ‘ZQC’ and the address signal ‘A10’ are in a high level and this defines a first carried out code calibration after the power-up. The code calibration time control command ‘ZQINIT’ may give instructions to carry out the code calibration for 512 cycles of the external clock ‘CLK’.
In the case where both the code calibration command ‘ZQC’ and the address signal ‘A10’ are in a high level, the code calibration time control command ‘ZQOPER’ is activated. However, the code calibration time control command ‘ZQOPER’ defines a code calibration after the first code calibration is carried out. The code calibration time control command ‘ZQOPER’ may give instructions to carry out the code calibration for 256 cycles of the external clock ‘CLK’.
The code calibration time control command ZQCS is activated when only the code calibration command ‘ZQC’ is in a high level, and may give instructions to carry out a code calibration for 64 cycles of the external clock ‘CLK’.
The external clock ‘CLK’ may be set up differently in time period within a predetermined range for operating features of a processor in a mobile apparatus.
As mentioned above, the code calibration time control commands ‘ZQINIT’, ‘ZQOPER’ and ‘ZQCS’ are executed during the cycles of the predetermined external clock ‘CLK’.
Accordingly, the longer the time period of the external clock ‘CLK’ is, the more it takes time to execute the code calibration and the more the power consumption is needed.
The conventional resistance calibration code generating apparatus has the following problems because it carries out the code calibration based on the external clock ‘CLK’.
First, since it takes a lot of time to execute the code calibration with the long time period of the external clock ‘CLK’, it has a disadvantage in terms of the operating time. Second, since the power consumption is increased with the long time period of the external clock ‘CLK’, an operating time in a portable device, in which a semiconductor integrated circuit is embedded with a battery, is decreased.